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CPU design
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121	LPDDR2 Memory Controller Design in a 28nm Process Behzad Boroujerdian Ben Keller Yunsup Lee Add to Reading List Source URL: www.eecs.berkeley.edu Language: English - Date: 2013-12-18 19:46:11 Dynamic random-access memory Memory controller CPU cache Mobile DDR Cell Random-access memory Memory bandwidth Prefetch buffer Synchronous dynamic random-access memory Computer memory Computer hardware Computing
122	PROJECT PROFILE 2A708: Low power expertise for mobile and multimedia system applications (LoMoSA+) EDA FOR SOC DESIGN AND DFM Add to Reading List Source URL: www.catrene.org Language: English - Date: 2009-03-25 10:35:47 ARM architecture Advanced Learning and Research Institute System on a chip ARM Holdings CPU design Application-specific integrated circuit Network On Chip MULTICUBE Electronic engineering Integrated circuits Electronics
123	Design Tradeoffs for Simplicity and Efficient Verification in the Execution Migration Machine Keun Sup Shim, Mieszko Lis, Myong Hyon Cho, Ilia Lebedev, Srinivas Devadas Massachusetts Institute of Technology, Cambridge, Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2013-08-26 16:12:52 Parallel computing Computer memory Central processing unit Computer architecture Microprocessors CPU cache Multi-core processor Cache Memory coherence Computing Concurrent computing Computer hardware
124	Design Space Exploration and Optimization of Path Oblivious RAM in Secure Processors Ling Ren, Xiangyao Yu, Christopher W. Fletcher ∗, Marten van Dijk and Srinivas Devadas MIT CSAIL, Cambridge, MA, USA {renling, yxy, c Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2013-04-22 20:42:08 Central processing unit Computer architecture CPU cache Cache Oram Dynamic random-access memory B-tree Microarchitecture Computer hardware Computer memory Computing
125	PDF Document Add to Reading List Source URL: s3.mentor.com.s3.amazonaws.com Language: English - Date: 2012-05-30 19:19:02 Mentor Graphics Electronic design automation Integrated circuit design Hardware description language Application-specific integrated circuit Logic synthesis Field-programmable gate array Functional verification CPU design Electronic engineering Electronic design Integrated circuits
126	The VLSI revolution at MIT by Paul Penfield, Jr. Remember the VLSI revolution? Add to Reading List Source URL: www.eecs.mit.edu Language: English - Date: 2014-05-05 15:32:09 Technology Women in technology Lynn Conway Women in engineering VLSI Project Very-large-scale integration Carver Mead PARC CPU design Electronic engineering Electronics Integrated circuits
127	Contents 1 Contract Postal Unit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1-1 Add to Reading List Source URL: www.savethepostoffice.com Language: English - Date: 2011-08-12 10:09:23 Central processing unit Contract Fixed price Scheduling Business Electronic engineering Management Contract law United States Postal Service CPU design
128	Hardware performance of eStream phase-III stream cipher candidates T. Good and M. Benaissa Department of Electrical & Electronic Engineering, University of Sheffield, Mappin Street, Sheffield, S1 3JD, UK {t.good, m.benai Add to Reading List Source URL: www.ecrypt.eu.org Language: English - Date: 2012-03-21 12:27:04 Trivium Throughput Computer performance Feedback with Carry Shift Registers F-FCSR CPU design Advanced Encryption Standard VHDL Grain Stream ciphers Cryptography ESTREAM
129	EECatalog SPECIAL FEATURE Conquering SWaP Challenges in Soldier-Wearable Applications Add to Reading List Source URL: www.connecttech.com Language: English - Date: 2011-08-29 11:09:05 Embedded systems Ambient intelligence Human–computer interaction Ubiquitous computing Wearable computer Quantum3D Computer-on-module CPU design PC/104 Computer hardware Classes of computers Computing
130	Invited paper presented at the 2nd Workshop on Complexity-Effective Design, Goteborg, Sweden, June[removed]Managing Complexity in the Piranha Server-Class Processor Design Luiz André Barroso, Kourosh Gharachorloo, Mosur R Add to Reading List Source URL: barroso.org Language: English - Date: 2005-03-07 23:37:58 Central processing unit Computer memory Logic design Microprocessors CPU cache Hardware description language Verilog Application-specific integrated circuit Multi-core processor Electronic engineering Computer architecture Computing

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